Clock extraction, also known as clock synchronization, is the name given to the process of regenerating a local clock signal from an incoming data stream, which is then used for sampling that data stream into a data buffer. Successful regeneration of the clock signal in a receiver ensures that a transmitted sequence of bits is correctly clocked into the receive buffer. FIG. 1 illustrates this by showing a waveform that is sampled by a bit clock that has a phase error with respect to the incoming data stream. Bit errors are more likely to occur around the edges of bits due to channel filtering, which means that the ideal sampling point is in the middle of each bit. In FIG. 1, the first stream from the top of the figure corresponds to the original data stream, the second stream corresponds to correctly sampled data stream and the last stream corresponds to incorrectly sampled data stream. In this example, the phase error has resulted in the sequence of bits 0110100010 being decoded as 0010000010.
There are various ways of extracting the clock signal from a received signal, all of which require that the incoming data stream has a reasonable number of transitions or edges. The edges are used as a reference point against which the local clock can adjust itself to obtain correct synchronization.
The requirement for these edges places a restriction on how the data is coded at the transmitter end. Raw data packets could contain any combination of bits, some of which may contain few if any edges. For this reason, for instance medium access control (MAC) protocols often add a preamble to the start of a packet that contains a known string of bits that contain a suitable number of edges. FIG. 2 shows a typical packet header structure comprising such a header. Preambles are used by the clock extraction circuit to obtain correlation before the raw data arrives, therefore ensuring that data can be decoded correctly once the data arrives. The preamble advantageously contains a sequence of bits in which zero and one bits (hereinafter referred to as 0's and 1's) alternate to provide a maximum number of edges. An example of a typical preamble is: 10101010. The longer the preamble, the better the synchronization is that can be achieved by a suitable clock extraction circuit.
For long packets, it is sometimes beneficial to continue clock extraction from the incoming data stream. This can be achieved for instance by using a digital phase locked loop (DPLL), for the duration of the whole packet. This ensures that any drift in the transmitter's clock, which becomes more noticeable in longer packets, is compensated for at the receiver. The disadvantage of this method is that DPLL must be running at its oversampling rate for the duration of the packet, therefore consuming more energy.
Once the bit clock has been correctly obtained, it is necessary to synchronize the receiver at word level. This is usually achieved using a synchronization word transmitted just after the preamble as shown in FIG. 2. The receiver, having achieved bit synchronization, monitors reception of the known synchronization word. At this point, it is then able to successfully process any data that follows. The synchronization word should be designed in such a way as to be robust to bit errors causing errors which lead to non-recoverable packet errors.
However, any extra information that is added to the transmitted data represents an undesirable overhead in transmission due to the extra energy and time required to transmit it. Minimizing these overheads is a key part of protocol design.
It is usual in communication systems for messages to be destined for a particular recipient. To enable suitable delivery mechanisms, devices are often given an address, which can be used by other devices to communicate with it. It is common practice to design transmission protocols which place the destination address shortly after the synchronization word in the data packet to enable receiving nodes to power down as quickly as possible if the message isn't destined for them. A possible optimization of this is therefore to use the device address as the synchronization word. In this way, a match with the synchronization word not only indicates time alignment to the receiving device but further indicates that the packet is destined for it.
The invention aims at providing a new packet header structure with minimal overhead and thus leading to power reductions. The invention also provides an effective way of detecting the packet header structure.